Readable Verilog Generator

What it does

• Confirms the design contract (ports, clock/reset, pipeline, interface family, verification cases), then produces a Python semantic model before emitting synthesizable Verilog-2001 .v files.
• Runs a formatter-backed quality gate with an eight-item matrix — compile / ast / readability / comment / naming / profile / testbench / toolchain — and publishes JSON + Markdown reports with VG rule IDs, locations and ordered repair steps.
• Handles existing RTL: structural analysis, semantic equivalence comparison, log-driven diagnosis and minimal evidence-backed patches (conservative, semi_auto, auto_apply).
• Emits a companion <module>_spec.md plus WaveDrom timing diagrams (JSON5 + SVG) for every module.
• Prefers real external evidence (Vivado xsim, VCS+Verdi, iverilog) and explicitly forbids claiming an unrun check passed.

Who it's for

• FPGA/ASIC digital design engineers who want consistent, reviewable RTL style.
• Teams inheriting legacy Verilog that needs structural analysis and semantic comments.
• Groups enforcing three-process FSMs, AXI-Stream/AXI4-Lite/AHB/APB templates and naming conventions.

Examples

1. "Write a 4-stage pipelined FIR module with an AXI-Stream interface" → requirements → codegen plan → spec document → RTL plus timing diagrams.
2. Hand it an existing uart_rx.v and ask for semantic comments only → the comment-only workflow proves token equivalence against an immutable normalized baseline.
3. Run python -m scripts.python.validation.generated_deliverable_gate rtl/ --json report.json --markdown report.md before hand-off to see every violation and its fix order.

Read the instructions in this file and follow them to help me:
https://raw.githubusercontent.com/Eriemon/verilog-generator/HEAD/SKILL.md

What I want: (describe your task here)

Install the skill I found on Claude Skill Mart.
Copy the SKILL.m folder from the GitHub repo Eriemon/verilog-generator into my ~/.claude/skills/readable-verilog-generator/.
When it's done, tell me in one line what this skill can do.